Introducing AMD Vitis Hardware in the Loop Validate Faster. Deliver Sooner. AMD Vitis Hardware in the Loop (Vitis HIL) bridges simulation and hardware bring-up by enabling system-level verification on evaluation hardware directly from existing MATLAB® or Python test environments. Teams can reuse familiar testbenches, stimulus generation, reference models, and result-analysis workflows instead of rebuilding them for hardware validation. Rather than replacing simulation, Vitis HIL extends verification to real silicon when greater speed, scale, or hardware fidelity is required. Software-Only Simulation for Heterogeneous Systems Can Be Complicated Consider a representative heterogeneous DSP design: a polyphase channelizer implemented across AI Engine kernels and HLS-compiled programmable logic (PL) fabric on an AMD Versal VC1902 adaptive SoC. The design operates at an 8.75 GHz input sample rate and produces 16 sub-channel outputs. End-to-end verification with the AI Engine simulator or cycle-accurate RTL simulation requires millions of input samples to confirm convergence, sub-channel separation, and spectral fidelity across operating conditions. Processing these realistic data sets in software can take a long time, whereas the same workload runs much faster on the target hardware. As a result, exploring parameters such as cascade length, SSR factor, and twiddle precision through simulation alone becomes impractical. Software simulation must model every pipeline stage, memory access, and inter-kernel data transfer, while the AI Engine array executes these operations in parallel at 1.25 GHz with deterministic, cycle-accurate timing. For the 16-channel polyphase channelizer described above, the clearest way to verify sub-band separation and phase alignment at the target sample rate is to run the design on silicon and observe the output directly. Vitis HIL runs the design on physical silicon rather than emulating it or relying on a behavioral model. AI Engine kernels execute on the physical AI Engine array at the programmed clock frequency (typically 1.25 GHz) on the VCK190, while the PL fabric runs at its synthesized clock rates. Memory accesses use the actual programmable NoC and block RAM hierarchy. As a result, host-side observations capture real pipeline latency, fixed-point rounding, saturation behavior, and timing-dependent edge cases that software simulation may not reveal. For complex DSP applications, hardware-speed execution makes measured performance directly representative of deployment. A polyphase filter bank using 400 AI Engine tiles at 1.25 GHz processes test vectors at hardware speed, so the latency and throughput measured with Vitis HIL are the values the deployed system will exhibit, not estimates derived from simulation cycle counts. How It Works in 10 Steps The Vitis HIL workflow has two phases. Phase 1 is a one-time build and board setup process. Phase 2 is the iterative test loop used as the design evolves. Engineers repeat Phase 1 only when the hardware architecture changes, not during routine test iterations. Phase 1: Set Up Configure a Vitis Subsystem with your AI Engine and programmable logic content Generate a bootable SD card image using a single build command Flash the image onto an SD card Insert the SD card and power on the development board Start the Vitis HIL server on the board Phase 2: Test Generate stimulus frames on the host using existing MATLAB® or Python scripts. Input data is wrapped in typed frame objects aligned to the Vitis HIL interface specification: no format conversion is needed. Call the Vitis HIL run function with the input frame list. The client marshals the data over TCP, initiates a DMA transfer to the AI Engine PLIO interfaces, and waits for the output. The AI Engine array and PL fabric execute the computation at the full silicon clock rate. Output data accumulates in DMA output buffers on the board. The run call returns with processed output frames. A drain loop at the end of a