After planar transistors gave way to FinFETs and FinFETs to gate-all-around nanosheets, the next transistor architecture is coming into focus: the complementary FET, or CFET, which stacks n-type and p-type transistors on top of each other to build the same logic in roughly half the footprint. Intel, TSMC, Samsung and IBM Research have now all put working silicon behind the concept. This conference report traces the progress from the December 2023 IEDM, where Intel, Samsung and TSMC first presented CFET data at the same meeting, to the 2026 VLSI Symposium, where Intel showed CFET inverters with PowerVia backside power at a 45nm gate pitch and Samsung reported three nanosheet channels per device at a 42nm gate pitch. Three of the four use monolithic integration, while IBM’s Nanostack roadmap relies on a sequential approach that bonds separately built tiers to sidestep thermal budget limits. Every group still faces hard process problems, from contacting the buried bottom transistor to etch selectivity between stacked channels. Published estimates put CFET in production logic in the early 2030s, but the move from device concepts to working circuits at back-to-back conferences signals where leading-edge logic is headed once gate-all-around runs its course. Click here to read the full article in Semiconductor Digest magazine. The post Stacking Up: Inside the Industry’s Race to Build CFET Transistors appeared first on Semiconductor Digest .