Micron doesn’t plan to adopt 4F² DRAM, arguing that its added complexity and cost don’t offer a viable scaling path. Speaking at a technology webinar, chief technology and products officer Scott DeBoer said the company has investigated the approach for two decades and built multiple prototypes. Instead, Micron intends to continue shrinking its existing DRAM architecture while developing 3D DRAM in parallel. The announcement follows CXMT’s plan to launch DDR5 registered memory modules for servers based on the 4F² architecture by year-end. The Chinese firm is the first memory maker to share a concrete 4F² path. This has been described as proof of China’s rapid progress in semiconductor manufacturing. Micron’s DRAM roadmap. Source: Micron The 4F² layout describes the area occupied by a memory cell, with F representing the process’ minimum feature size. A 4F² cell occupies four times the square of that size, compared with six times for today’s common 6F² designs. At the same feature size, this makes each cell one-third smaller and could fit 50 percent more cells into the same array area. As DeBoer explained during the webinar, however, cell size isn’t everything. “It’s a bit of a myth that 4F² provides anything versus 6F². It’s the capacitor pitch that defines the DRAM. You can build the cells, the transistors in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM. So, some of that is just kind of smoke and mirrors in terms of talking about 4F² versus 6F².” DeBoer said 4F² can be manufactured at older nodes, but encounters fundamental physical limitations when scaled beyond Micron’s current technology. He didn’t specify those limitations in the webinar. Micron expects several more conventional DRAM generations, incorporating wafer bonding, new materials and high-NA EUV, before introducing 3D DRAM when its cost and performance justify the transition.