By Anand Murthy Training and deploying large AI models requires unprecedented computing power, memory bandwidth, and energy efficiency. Meeting those demands is no longer just about scaling transistors. Increasingly, it is about how chips are designed, connected, packaged, and manufactured as complete systems. The industry’s answer is taking shape in three dimensions. 3D integration, advanced packaging, next-generation memory architectures, and new patterning technologies are emerging as critical enablers of AI computing. Together, they allow chipmakers to break through traditional scaling constraints and deliver the performance gains required for the AI era. In this context, Lam has extended its long-standing strategic collaboration with imec, a world-leading research and innovation center in advanced semiconductor technologies, to include two new joint research and development focuses: enabling advanced 3D integration and advancing Aether® dry resist for future high-NA EUV patterning. AI Is Redefining How Semiconductor Performance Scales The most advanced AI systems rely on tightly integrated combinations of logic, memory, and interconnect technologies. Moving data efficiently between these elements has become just as important as improving individual transistor performance. That reality is driving increased adoption of advanced packaging and chiplet architectures that combine multiple specialized chips into a single system. Three-dimensional integration allows chipmakers to increase performance, memory capacity, and bandwidth while improving energy efficiency. As traditional transistor scaling becomes more challenging, advanced packaging has become a critical path for extending semiconductor performance. But making these architectures manufacturable at scale requires innovation across materials, deposition, etch, patterning, and integration. This is where collaborative innovation becomes essential. Lam and imec Advance Manufacturing Readiness for 3D Integration Lam and imec are collaborating to accelerate manufacturing readiness for 3D integration technologies supporting advanced packaging and next-generation memory. By bringing together Lam’s deep capabilities in deposition and etch with imec’s world-class integration infrastructure, the collaboration is designed to boost the velocity with which promising innovations move from the lab to high-volume manufacturing. The collaboration focuses on key process challenges that must be solved before heterogeneous integration can scale broadly across the industry. Areas of joint research include thick dielectric deposition, asymmetric stress compensation, bevel deposition, and plasma dicing, alongside process validation for advanced packaging and future memory architectures. The work also extends into future 3D memory technologies, including new charge-trap materials, precision multilayer deposition, high-aspect-ratio channel etch, deep memory contacts, and low-resistivity interconnects. These innovations are increasingly important as AI workloads drive demand for greater memory density and bandwidth. Aether Dry Resist Enables the Next Era of High-NA EUV Patterning While advanced packaging and 3D integration help scale systems, AI also depends on continued advances in leading-edge logic devices. As the industry approaches angstrom-era nodes, high-NA EUV lithography is required to enable smaller features and increased transistor density. However, high-NA EUV requires innovations in related technologies in resists, mask design, patterning, materials, deposition, etch, and device integration. To address these challenges, Lam and imec are also collaborating on research and development to advance the application of Lam’s Aether dry resist platform. Using imec’s high-NA EUV research environment, the joint work is focused on enhancing resolution, sensitivity, depth of focus and stochastic defectivity. The collaboration includes exploring Aether-enabled patterning for advanced interconnect