Key Takeaways: Moving advanced packaging from wafer to panel changes more than available area. Processes developed around wafer geometry, handling, and equipment have to be reconsidered at panel scale. Larger panels amplify dimensional change, warpage, and process history, making what happens at one manufacturing step increasingly important to the next. The most economical manufacturing flow may use different substrate formats at different stages rather than carrying one large panel through the entire process. Moving advanced packaging from wafer to panel sounds, at first, like a geometry problem. Large AI and HPC packages are increasingly rectangular, while the 300mm wafer underneath them is still round. As the package size grows, more of that expensive processing ends up around the circle’s edges where nothing useful can be built. A panel gives that area back. It can fit more large packages into the same process cycle, and unlike a wafer, its dimensions don’t impose the same hard limit on the size of a square or rectangular package. For advanced packages that keep getting larger, the economics are difficult to ignore. But the semiconductor packaging sector has spent decades learning how to process wafers, not panels. Equipment, materials, recipes, handling systems, and process controls were all developed around the geometry and mechanical behavior of a round workpiece. “The risk of doing the assembly on the 600mm panel is high, and I don’t think we have all the equipment today to run the process,” said Teck Chong Lee, technical director of advanced fan-out development for HPC applications at ASE , in a recent presentation. “One of the options is, once you complete the interposer in large format in 600, then you divide it into four pieces to run the assembly and the C4 process. This is a much lower-risk approach.” The economics behind that compromise are substantial. In the same study, a 5.5×-reticle-size interposer produced 9 units on a 300mm wafer, compared with 16 on a 300mm panel. A 600mm panel divided into four 300mm pieces produces 64, while processing the full 600mm area intact raises that to 72. In pure utilization, the intact panel produces 8 times as many units as the wafer, a gain well beyond the roughly fivefold difference in raw area, because the rectangular panel wastes almost nothing at its edges. The flow therefore takes the area advantage where it can use it, then gives some of it back before assembly because the manufacturing infrastructure isn’t ready to follow the larger format all the way through. That compromise exposes the larger transition underway. Moving packaging from wafer to panel isn’t simply making the process bigger. It is discovering which parts of the process were dependent on the wafer dimensions all along. The process was built around the wafer The utilization advantage grows as the package does. In one comparison, Intel Foundry used a 510 × 515mm panel and showed that a roughly 4× reticle package would produce about 10 units on a 300mm wafer and approximately 48 on the panel. Eventually the wafer imposes a harder geometric limit, since the largest square that fits on a 300mm wafer is only about 210 × 210mm. “For certain form factors, we believe a wafer is more economical,” said Tarik Ibrahim, senior principal engineer at Intel , in a conference presentation. “However, when you go beyond a certain form factor, you can see quickly that the panel becomes more effective, mainly because you can get more units out of a panel. Because of the way AI is heading and the need for a very large system, panels became an obvious choice for scale.” Fig. 1: Intel’s Tarik Ibrahim discusses substrate scaling for heterogeneous integration. Source: Semiconductor Engineering The economic crossover doesn’t mean the manufacturing process crosses over with it. Much of the equipment and process knowledge used in advanced packaging was developed for a round wafer, and changing the shape and scale of the substrate ch