For decades, silicon characterization has been built around Process, Voltage, and Temperature, or PVT. We characterize devices across process variation, sweep voltage and frequency, control temperature, generate SHMOO plots, and establish the operating envelope of the silicon. That methodology remains fundamental. But today’s high-performance processors are increasingly systems in their own right. An AI accelerator may contain thousands of compute elements, distributed SRAM, high-speed SerDes, PCIe and Ethernet interfaces, multiple clock and power domains, advanced packaging, firmware, operating systems, compilers and application software. Two devices operating at exactly the same voltage, frequency, and temperature can behave differently depending on what they are being asked to do. This suggests adding another dimension: PVTW: Process × Voltage × Temperature × Workload Frequency can be swept within this characterization space to determine operating margin. The objective is not to replace traditional ATE characterization with System Level Test. It is to combine the electrical precision and control available from ATE with the realistic operating environment available from SLT, while retaining the ability to use either independently. One platform, two capabilities, three modes One way to implement PVTW is through a hybrid characterization architecture integrating ATE resources and SLT capability. There is no reason to recreate resources that already exist in ATE. Existing ATE infrastructure, including older generation platforms, can provide programmable device power supplies, individual rail control and measurement, variable frequency clocks, digital stimulus and capture, ATPG and structural content, parametric measurements, and conventional SHMOO characterization. SLT provides something fundamentally different: the application environment. The processor can boot firmware and an operating system, load drivers and runtime software, and execute deterministic workloads designed to exercise specific parts of the architecture. For an AI processor, those workloads might emphasize compute, SRAM, external memory, PCIe, Ethernet, or chip-to-chip communication. Other workloads could intentionally activate several simultaneously to create realistic system stress. The architecture therefore provides three modes. ATE mode performs conventional electrical, structural, and parametric characterization. SLT mode executes controlled system workloads. Combined mode uses ATE resources to control and measure electrical conditions while the device executes an SLT workload. Combined mode is where PVTW becomes particularly interesting. From conventional SHMOO to workload SHMOO Consider a conventional voltage and frequency SHMOO using ATPG or appropriate functional content. At a controlled temperature, establish the operating boundary. Now boot the processor, establish a deterministic workload, and repeat the sweep. Start with a compute-intensive workload. Repeat with SRAM, external memory, PCIe, and Ethernet-intensive workloads. Finally, create combinations that deliberately generate simultaneous compute, memory, and I/O activity. Suppose an ATPG SHMOO indicates that a device operates correctly down to 0.72 V at a particular frequency, while an SRAM-intensive application begins producing errors at 0.76 V. That 40 mV difference is not simply a disagreement between ATE and SLT. It is characterization information. Something about the workload is consuming margin. Is it SRAM timing? Clock distribution? IR drop? Simultaneous switching noise? A thermal gradient? Power delivery? Or an interaction among several subsystems? Characterization requires control There is an important distinction between testing and characterization. Booting Linux, running an AI workload, and observing whether the processor crashes is useful testing. Characterization requires controlled variables, repeatability, and the ability to deliberately move the operating boundary. Hold workl