ALEX SHAPOVAL , Eyelit Technologies Semiconductor fabs reduce cycle time mainly by cutting the time wafers spend waiting. Faster processing helps much less. At an X-factor of 3, where cycle time is three times raw process time, only a third of a wafer’s time in the line is spent being processed. The rest is non-processing time: queuing, waiting for batches, moving between tools or sitting on hold. Dispatching, finite-capacity scheduling, the manufacturing execution system (MES), advanced process control (APC) and simulation each go after a different share of that waiting. A dispatcher picks the next lot at a tool, and a scheduler plans tool loading a few hours out. The MES holds the record of where every lot and tool stands. APC cuts the rework and excursions that send lots back through the line, and simulation lets engineers try out policy changes before the fab floor sees them. All five depend on accurate WIP and equipment-state data, and none of them works well without it. Where cycle time builds up Most cycle time builds up in queues at heavily loaded tool groups, and reentrant flow multiplies the effect. Two standard results from factory physics show why. Little’s Law says cycle time equals WIP divided by throughput, so at constant output, cutting WIP in the line by 10% cuts cycle time by 10% [1]. Kingman’s approximation says queue time at a tool group depends on variability, process time and a utilization term, u/(1 − u), where u is utilization [2]. The utilization term is 5.7 at 85% utilization and 19 at 95%. Moving a tool group from 85% to 95% loading therefore makes that part of the formula more than three times larger, and if variability and process time stay the same, expected queue time grows by the same factor. Reentrant flow makes these queues compound. McKinsey describes semiconductor manufacturing as iterative, with hundreds of steps and thousands of equipment chambers, and wafers revisiting the same equipment multiple times [3]. Lithography alone sees each wafer once per patterned layer. So when one tool group slows down, the same lot is delayed at every visit, along with every other lot waiting for that group. Other waits sit on top of this. Lots wait at batch tools such as furnaces and wet benches until the batch is full. Queue-time limits between steps, such as clean-to-furnace windows, turn a late lot into a rework lot. Engineering and quality holds add their own delay, as do transport and material handling. Matching each approach to the waiting it can reach Fabs improve throughput and cycle time by aiming each approach at the part of the waiting it can reach. TABLE 1 sets out what each one controls and how far ahead it looks. Table 1. What each approach controls Approach What it controls Time frame Main effect on cycle time Dispatching Which lot runs next at a tool Seconds to minutes Cuts queue time at bottlenecks by sequencing lots well at each tool Finite-capacity scheduling Tool loading, setups, batches and queue-time limits Hours to one shift Cuts batch waits, setups and queue-time violations by planning ahead MES Lot, recipe, hold and equipment-state records Continuous Cuts hold time and paper delays, and supplies the data the other tools use APC Run-to-run control and fault detection Per run Cuts rework loops, excursions and unnecessary measurement steps Simulation Start rates, WIP levels, dispatch rules, capacity Weeks to years Finds the policy changes that shift the whole fab’s operating point Dispatching Dispatching decides which lot a tool runs next. At bottleneck tools, where queues are longest, that choice has the largest effect on cycle time. Real-time dispatchers rank the waiting lots by rules such as first-in-first-out, critical ratio, earliest due date, setup avoidance and WIP line balance. Good rules at constrained tool groups lower average queue time and narrow its spread. The limit is that a dispatcher looks only one decision ahead. It has no way to know that the lot it starts now will