Even silicon starts behaving like rubber on a microscopic level. As hybrid bonding moves toward pitches of 1 micrometer and below, tiny deformations become a major obstacle. Research by Besi and Imec shows why mastering the process is just as important as building a highly accurate bonding machine. Hybrid bonding takes place in a micro- and nanoworld in which the elastic behavior of presumably hard materials such as silicon and gallium arsenide starts becoming noticeable. The complex interaction of mechanical stress, thermal effects and bonding forces makes the introduction of this technology quite challenging. To provide some insight, Bits&Chips revisits a presentation given by Jonathan Abdilla, Director CTO Office at Besi, at the 3D & Systems Summit in Dresden in 2025. What he presented was the result of close collaboration with Imec in Leuven. The research is now a few years old, but Abdilla’s presentation clearly illustrates where the biggest challenges in advanced packaging lie. It shows the accuracy and process control required for hybrid bonding at ever-smaller pitches. Alignment accuracy is shifting from micrometers to nanometers: Bond pitches are moving toward 1 micrometer (µm) and below, where even minimal overlay deviations can lead to yield loss. Many factors influence the shape of a chip during the hybrid-bonding placement process. Credit: Applied Materials/Besi Detailed model In hybrid bonding, Besi specializes in equipment for die-to-wafer. In this process, chips are placed one by one onto a wafer. This is done without solder or adhesives. The bare, extremely flat and very clean surfaces bond immediately through Van der Waals forces – a process that doesn’t allow corrections. The dielectric bond is then reinforced through annealing and shifts to a strong covalent bond. The opposing copper pads come into contact and fuse with each other after a higher-temperature annealing step. At this level, shrinking or stretching of the chip (the rubber-like behavior on a nano scale) affects the bonding process during placement. This phenomenon, die scaling, is an important limiting factor for overlay accuracy. It’s determined by a complex interaction of mechanical stress, thermal effects, bonding forces and machine design, among other factors. Together, these factors determine the total overlay error budget. Abdilla: “We’re used to considering silicon dies as non-elastic, but once you start working at the nanometer scale, things turn out to be very different.” The Besi and Imec teams systematically mapped all error sources individually. They distinguished between correctable errors, like machine calibration, and non-correctable ones, such as material variations and environmental influences. The latter are particularly problematic. For a better understanding, Besi and Imec developed a detailed model. It incorporates machine interactions, chip properties, the vacuum used (to hold the die by suction), bonding parameters and environmental conditions. The partners examine warpage (bending of the die due to material stress), surface activation and the force profile during bonding. All parameters, especially non-machine-controlled ones, vary continuously during the process. This makes it difficult to monitor and even worse to simulate effectively. In any case, the dynamic behavior underlines the need for integrated process optimization. Important parameters One of the most important phenomena to understand is warpage. The thinner the dies, the more susceptible they are to deformation. Greater warpage, in turn, results in lower positioning accuracy. In some instances, warpage increased from 2 to 30 µm when die thickness decreased from 310 to 50 µm. This translates directly into larger overlay errors. Process and chip design must therefore be optimized together. Existing designs can’t simply be reused for advanced hybrid bonding applications. Machine design plays a crucial role. The way a chip is held by suction and deformed during t