Future Transistor Stacking Plans Start to Diverge

Chipmakers agree that the transistor of the next decade will actually be two transistors stacked atop one another, packing in many more devices in the same area of silicon and leading to circuits that are as little as half the size of today’s. But their research efforts are beginning to show some important divergence in the details. Commercial introduction is likely six years away, so they are far from a final version, but research presented last week at IEEE VLSI Symposium in Honolulu and detailed today by IBM points toward two main paths. Though companies have different names for it, in research this future device is commonly called the CFET, for complementary field-effect transistor . It takes the two types of transistor, the p -channel and n -channel field-effect transistor (PFET and N