Advanced packaging has a bigger place at SEMICON West than ever, with three days of packaging content on this year’s program, and SEMI is building a global home for the topic through its Advanced Packaging and Heterogeneous Integration (APHI) technology coalition. “We’ve never had this much, and it shows how we’re evolving with the industry,” Joe Stockunas, president of SEMI Americas, said at Monday’s SEMICON West press conference. Beth Keser, who joined SEMI about five weeks ago as vice president of technology coalitions, is leading the effort. Keser has worked in advanced packaging for more than 30 years at Motorola, Qualcomm, Intel and two startups, most recently a photonics startup in San Francisco. She spent 10 years on the IEEE Electronics Packaging Society board of governors, was general chair of ECTC in 2015 and served as president of IMAPS from 2021 to 2023. Packaging and test are becoming more important “as we disaggregate our chips into chiplets and then recombine them in advanced packaging, whether you’re doing 2.5D, 3D or 2.xD,” she said. Photonics, she added, will also be a big part of the journey. A precompetitive home for packaging APHI is one of 20 technology coalitions Keser oversees. Its aim is to support global, precompetitive technology development and innovation for manufacturing readiness, and to drive consensus, adoption and interoperability of design-enabling packaging technologies and standards so that electronic and photonic systems reach market faster. The coalition’s work includes industry leadership, public-private R&D projects and global standards. SEMI has also funded the Heterogeneous Integration Roadmap (HIR), together with IEEE and ASME, since 2016; the open-access roadmap is revised every other year. APHI began about three years ago at SEMI’s headquarters in Milpitas, Calif. SEMI is now bringing an APHI Summit to its SEMICON events in the Americas, Europe, India, Southeast Asia, Korea, Japan, China and Taiwan, along with smaller regional events. In 2027, the calendar includes APHI Summits at SEMICON China, SEMICON West, SEMICON Southeast Asia, SEMICON Taiwan, SEMICON India and SEMICON Europa, as well as in Korea in July. The goal, Keser said, is for attendees worldwide to see SEMI as a place to go for packaging, “and not just front end.” Glass substrates by 2028 Asked when glass core substrates will make an impact, Keser said sooner than she once expected. Glass stays flat, avoiding the thermal expansion mismatch and warpage of organic cores, supports finer lines and spaces, and can be tuned for thermal expansion and elastic modulus. The hard part is the vias. Glass can’t be mechanically drilled without shattering, so high-aspectratio vias must be chemically etched or formed with a combined laser and chemical process, then plated, much like through-silicon vias. Intel has said it worked on the technology for a decade. “Two years ago I would have said 2030, but because these package sizes are getting so large, I would say 2028,” Keser said. She expects a few leaders to take the risk first, followed by fast followers, much as TSMC was for years the only company doing silicon interposers. Bridges, panels and energy per bit In the near term, Keser expects more bridge-based interconnects. Silicon interposers have provided highdensity interconnect since TSMC’s CoWoS arrived in 2012, but interposer capacity is limited, pushing the industry toward bridges such as Intel’s embedded bridge in the substrate and OSATs’ own versions, increasingly embedded in mold compound for fan-out wafer-level packaging. Because few large packages or interposers fit on a round 300mm wafer, she sees a move to 310mm x 310mm square panels, led by TSMC and ASE, and eventually to 510mm x 515mm or 600mm x 600mm. The defining trend, she said, is energy efficiency in the data center: low-energy interconnects between chiplets that lower energy per bit and, with it, the power and cooling these systems require. The post SEMI Build