ChipAgents , the category leader in agentic AI platforms for semiconductor design, announced the expansion of its AI-native engineering platform across digital and analog chip design, bringing more of the semiconductor development flow onto a shared agentic foundation. AI models are evolving on a months-long cadence, while traditional chip development can take 12–18 months or longer. Building the next generation of custom silicon for AI requires engineering teams to move faster across increasingly complex digital and analog design cycles. Yet much of that work still happens across fragmented tools, teams and workflows, forcing engineers to manually carry context from one stage of the design process to the next. ChipAgents’ full-stack approach enables engineers to define objectives, constraints and critical judgment calls while AI agents carry more of the execution forward, reasoning over design context, operating engineering tools, evaluating results and determining the next action toward closure. “Autonomous semiconductor engineering is a systems problem,” said William Wang, founder and CEO of ChipAgents. “It is not enough to make an individual model stronger or add more agents to a workflow. The AI needs to understand the organization’s design knowledge, coordinate the right models and tools, evaluate real engineering results and account for the physical consequences of each decision. We built ChipAgents around that entire system so engineers can focus on the design objective while AI handles more of the execution underneath.” Powering the platform is IC-star, ChipAgents’ chip neural engine for digital and analog semiconductor engineering. IC-star is designed to navigate the enormous semiconductor design space by evaluating the current design state and determining the next best action rather than requiring engineers to manually decide which model, tool or workflow to run next. IC-star brings together four tightly integrated capabilities: IC Design Ontology: A persistent context layer for engineers and agents that unifies design knowledge, plans, reusable skills and customer-specific methodologies, continuously improving the system through engineering feedback. Reasoning Core: Plans and coordinates agents, models and engineering tools around an objective to execute long-horizon workflows such as root-cause analysis, PPA-aware RTL closure and analog layout generation. Multiphysics-Aware Models: Predict timing, PPA, DRC, DFT and analog physical design to enable multi-objective co-optimization at generation time. Renoir, ChipAgents’ semiconductor-specific, physics-aware LLM, serves as a core domain model within this layer. Design-Driven Model Navigator: Dynamically routes work across AI models based on the task, balancing quality of results, time to results and cost. Together, those capabilities allow ChipAgents to co-optimize model choice, token consumption, tool execution, engineering review and physical feedback around the total engineering outcome, rather than optimizing each AI task independently. ChipAgents measures value in the time it takes for designs to converge, engineering effort and overall execution costs across both digital and analog chip design. The same foundation spans both digital and analog engineering. Digital workflows supported by ChipAgents include specification analysis, architecture exploration, RTL design, functional and formal verification, root-cause analysis and debug, coverage closure and PPA-aware optimization. Analog workflows extend across topology and schematic design, simulation, behavioral modeling, layout generation and physical verification. ChipAgents is expanding its collaboration with NVIDIA to fine-tune Nemotron models for AI-native digital and analog design workflows. ChipAgents reports initial results show that the post-trained Nemotron model achieves performance competitive with frontier models, including Fable 5.1 and GPT-6 Astra, based on open benchmarks, while delivering the high