This is the tenth part in a series on how AI is crossing out of software and into the physical world. This time, Jan Bosch looks at AI designing the hardware that AI runs on, and what happens to engineering when iteration becomes almost free. In 2021, a Nature paper from Google described a reinforcement learning agent that could place the macros on a chip in under six hours, with better power, timing and area than human engineers achieved. The self-improving loop had apparently closed: Better chips train better models, which design better chips. Five years on, that result is the most disputed claim in the field, and the shape of the dispute turns out to be more instructive than the result would have been. This Alphachip controversy ) is worth recounting precisely, because it’s easy to tell badly in either direction. A Google engineer, Satrajit Chatterjee, produced an internal analysis arguing that conventional methods did better; Google declined to publish it, his employment ended and he sued, alleging misconduct. Chung-Kuan Cheng and Andrew Kahng at UC San Diego re-implemented the method and reported that it didn’t beat simulated annealing, an academic placer, a commercial placer or human placement. In a 2025 update, it was confirmed that for full routing, it never produced shorter wire length than the commercial tool while using far more computation. Igor Markov published a critique in Communications of the ACM alleging cherry-picked benchmarks and selective baselines; ACM attached an expression of concern to it. Google’s authors reject all of this, and not without argument. Their position, set out in a paper pointedly titled “That chip has sailed,” is that critics skipped the pre-training step that makes the method work and used insufficient compute. Nature published an addendum in 2024 adding missing methodological detail. The critics reply that the compute they used matched the paper. I’m not going to adjudicate it, and I don’t think anyone reading this can. That’s the point. Because notice what’s actually missing. The training data was proprietary. The pre-training inputs were never released. There’s no common public benchmark on which the competing claims can be run side by side. Five years, a lawsuit, a journal addendum, an ACM expression of concern, and the reason it can’t be settled isn’t that the science is subtle; it’s that the evidence required to settle it doesn’t exist in a form anyone outside one company can use. And this isn’t confined to the disputed case. Cadence states that Cerebrus has been used on more than a thousand production designs. Synopsys reported a hundred commercial tapeouts for DSO.ai, with up to 15 percent power reduction and better than threefold productivity gains, and says nine of its top ten digital-implementation customers are adopting its AI technology. These are probably all true. They’re also not comparable: The definitions of “design,” “tapeout” and “AI-driven” differ between vendors and public evidence correlating these claims with production results at advanced nodes is, as far as I can find, absent. A Synopsys executive remarked this year that reinforcement learning in core EDA algorithms, meaning placement and routing itself, “hasn’t really panned out,” which, from a vendor selling AI-driven EDA, is a usefully candid distinction between AI in the flow and AI replacing the optimizer. So, let me separate what happened from what was announced, because something real did happen. AI didn’t arrive in design as a better decision-maker; it arrived as a cheaper search. The optimizers that place and route a chip were already extremely good; what was expensive was exploring the space of possible configurations: trying a hundred floorplans, sweeping constraint sets, testing architectural variants before committing. That exploration used to cost engineer-weeks. It now costs compute. Siemens has just agreed to buy Precision Innovations, the commercial company around the open-source Openroad flo