Researchers at Arizona State University and University of Maryland published “SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators.” Abstract : “Heterogeneous 3-D compute-in-memory architectures can combine different memory technologies across stacked tiers to accelerate deep neural network inference, but multitenant deployments introduce security risks through shared power delivery networks. The researchers developed SEAL, a security-aware layer-mapping framework that jointly optimizes power, performance, area, and fault vulnerability by assigning critical neural-network layers to more fault-resilient device and tier combinations. Evaluations using ResNet-18 and Qwen2.5-3B showed reductions in fault vulnerability of up to 3.9× and 7.8×, respectively, compared with security-blind mapping where both approaches produced usable mappings. In ReRAM-heavy configurations, SEAL placed all high-criticality layers on low-vulnerability tiers and reduced fault vulnerability to the characterization floor. ResNet-18 accuracy remained within 0.06 percentage points of the fault-free baseline, while Qwen2.5-3B perplexity remained within 0.06 of its fault-free baseline.” Find the technical paper here . September 2026 Sharma, Pragya, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, and Krishnendu Chakrabarty. “SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators.” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, September 2026. https://doi.org/10.1109/JXCDC.2026.3734047. License . The post Security-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland) appeared first on Semiconductor Engineering .