IBM and Siemens have announced a research collaboration to advance IBM’s 3D nanostack transistor architecture, targeting the design and manufacturing challenges of future angstrom-scale semiconductors . The partnership will combine IBM’s semiconductor research with Siemens’ electronic design automation (EDA), simulation and lithography expertise to help move the technology closer to commercial production. The collaboration could have significant implications for the European semiconductor industry, particularly as chipmakers look for new ways to extend transistor scaling beyond conventional designs. For eeNews Europe readers, the work highlights the growing importance of EDA tools and virtual manufacturing techniques in developing next-generation chips for AI and high-performance computing. Moving transistor scaling from 2D to 3D Unveiled earlier this year, IBM’s nanostack architecture uses vertically stacked and staggered nanosheet transistors to increase transistor density while improving performance and energy efficiency. According to IBM, the architecture can accommodate nearly 100 billion transistors in an area the size of a fingernail at its current 7-angstrom node. Unlike conventional transistor structures, nanostack also allows different semiconductor materials to be used within individual stacked layers. This enables engineers to optimize the power and performance characteristics of each transistor independently, potentially improving logic density and SRAM scaling. “Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade,” said Huiming Bu, Vice President of Silicon Technology R&D, IBM. Siemens EDA tools target manufacturing challenges Having demonstrated the feasibility of nanostack, IBM is now focusing on the design and fabrication challenges involved in scaling the architecture toward production. The collaboration will develop advanced virtual models to simulate transistor performance, optimize chip designs and identify potential manufacturing problems before physical devices are fabricated. Siemens will contribute its expertise in EDA software, process simulation, lithography optimization and manufacturing technologies, with the research extending beyond IBM’s current 7-angstrom generation. “Scaling semiconductors into the angstrom era demands tightly coupled co-optimization between device physics, EDA design and manufacturing software, and manufacturing. As physical AI places extraordinary demands on silicon architecture, IBM’s 3D nanostack design represents a pivotal leap forward,” said Ankur Gupta, Executive Vice President, EDA IC Portfolio, Siemens. Building a path toward production The companies aim to shorten development cycles by integrating device design, simulation and manufacturing considerations earlier in the research process. The collaboration reflects a broader industry shift toward co-optimizing transistor architectures and manufacturing processes as traditional scaling becomes increasingly complex. While IBM and Siemens have not announced a production timeline, the research could help establish the design and manufacturing capabilities needed to bring future generations of 3D nanostack chips into commercial fabrication. The post IBM and Siemens team up to advance 3D nanostack chip technology appeared first on eeNews Europe .