Key Takeaways: The semiconductor industry reached $1 trillion years early, but keeping pace with demand now depends on systems integration as much as transistor scaling. Packaging, photonics, power, and test are converging into one optimization problem, which means improving any one of them can move the bottleneck somewhere else. AI is shifting from the workload the industry serves to a tool it uses, and the open question is how much engineering and manufacturing authority it will be given. When SEMICON West gathered in San Francisco in 2023, the semiconductor industry was forecasting a path to $1 trillion in annual revenue by 2030. Three years later, the industry has already blown past that number. SEMICON West 2026 returned to San Francisco with a sold-out exhibit floor, more than 30,000 attendees, and an industry confronting a different question: How does it keep up with the growth it once aimed for? SEMI’s own projections show how steep that curve has become. In his opening keynote, SEMI President and CEO Ajit Manocha forecast a market of more than $2 trillion by 2030, and potentially $3 trillion by 2035. At the SEMI Market Symposium, the association projected 300mm fab equipment spending of $149 billion this year, rising to $227 billion by 2029, with construction beginning on 20 new 300mm fabs or production lines in 2026 alone. AI infrastructure is driving much of that growth, but electrification, autonomous vehicles, robotics, and industrial automation are adding semiconductor content, as well. What makes the current expansion unusual is the growing complexity of the systems those chips will enable, not the almost insatiable demand for chips. “We’ve started talking about how to re-engineer engineering because you need to co-design and optimize across multiple intersections,” said Sassine Ghazi, president and CEO of Synopsys . “That’s at the physics level, material, process technology, architecture, design, along with the software and the model itself, because the model itself is what’s defining the workload, and how do you optimize along that stack?” Across presentations, panels, and discussions on the show floor, several issues kept converging around that problem. Advanced packaging is becoming part of system architecture. Photonics is moving closer to compute, while bringing new manufacturing and test challenges with it. Test, inspection and metrology have to follow more complicated assemblies and manufacturing histories. And AI is moving from something the industry builds to something it uses to design and manufacture. None of these technologies is new, but each is becoming harder to optimize independently, and that may be the clearest indication of what the industry will be working on in the coming years. Scaling becomes a system-level challenge The shift was apparent in conversations ranging from transistor scaling and HBM to advanced packaging, optical interconnects, and cooling, where improving any one of those can move a bottleneck elsewhere. More compute increases pressure on memory bandwidth and power delivery. Moving memory closer reduces data movement but concentrates heat. Disaggregating a large die can improve yield and allow functions to use different process nodes, but it creates more interfaces that have to be connected, powered, cooled, and tested. “Packaging is no longer simply the place where semiconductor innovation ends,” said Lalitha Immaneni, vice president of semiconductor R&D at Intel Foundry . “Increasingly, it’s the place where system innovation begins.” That makes memory, data movement, power delivery, and thermal management part of the architecture rather than downstream considerations. “The challenge is not to co-optimize one component,” Immaneni said. “It is to co-optimize across the system from end to end between silicon, packaging, and platform.” Nitin Deshpande, Marvell’s vice president of advanced packaging, made a similar point during imec’s pre-show ITF USA program. “The package is r