At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography conference, an expert panel discussed the growing importance of edge placement error (EPE). I had the pleasure of joining moderator Jed Rankin of IBM and fellow panelists Hans Stiepan of Carl Zeiss SMT, Ezequiel Vidal-Russell of Micron Technology, Jo Finders of ASML, Il-Yong Jang of Tekscend, and Vivek Balasubramanian of Applied Materials. Together, we brought perspectives spanning OPC and EDA, mask technology, lithography systems, materials, and metrology. One point quickly became clear: EPE is no longer a narrow lithography metric. It is becoming a system-level measure of how well our industry can translate design intent into a manufacturable, high-yielding device. The mask, scanner, resist, etch process, metrology, OPC, and downstream integration all contribute. Each discipline can optimize its own part, but a collection of local optima does not automatically produce the best device—even if everyone arrives with an excellent slide explaining why their part is already optimized. EPE has become a system problem As pitch scaling becomes more difficult, tighter control of placement, variability, and pattern fidelity becomes one of the main paths to continued scaling. The challenge is that EPE is an unbounded budget. Mask three-dimensional effects, absorber profile, sidewall angle, critical-dimension uniformity, registration, scanner behavior, resist variability, etch, stochastic effects, process-induced stress, and even wafer or die bonding can all move an edge or change its electrical consequence. Yet the audience survey delivered a wonderfully familiar verdict: OPC was viewed both as a major source of EPE and as the leading place from which future EPE reduction would come. In other words, OPC was cast as both the villain and the superhero. Jed leaned into the joke, asking what Ezequiel and I would need from the rest of the industry to carry that superhero burden. By the final poll, confidence in OPC had risen to 58 percent—prompting the prediction that I might appear next time in tights. I am happy to accept the confidence; the cape may be negotiable. The EDA challenge: Stop treating residual error as one big bucket Today, many effects that are difficult to isolate are absorbed into empirical corrections, rule tables, or an “etch” term. This is pragmatic and often necessary in production, where repeatability, runtime, yield, and schedule outweigh a perfect explanation. Ezequiel captured the dilemma well: after seeing the poll, he was not sure whether the OPC community should feel encouraged or concerned. The audience clearly expected OPC to take care of every systematic and correctable effect—and, where possible, reduce sensitivity to the uncorrectable ones too. That is an impressive job description for any superhero. But even OPC needs good physics, good data, and a process window; it cannot leap an inaccurate model in a single bound. As tolerances shrink, the effects we sweep into the correction bucket become large relative to the remaining process window. EDA must therefore represent the real manufacturing system more completely: not an idealized mask with uniform properties, but pattern-dependent mask profiles, realistic metrology behavior, scanner effects, process variability, and the interactions among them. Not more data, better data More data alone is not the answer. We need data that is physically meaningful, sufficiently repeatable for manufacturing, and connected to the patterns that matter on the wafer. A single SEM image contains far more information than one extracted CD. Contours, profiles, roughness, placement, local geometry, and pattern context can all inform better models. At the same time, no fab can measure everything. OPC and process models should help identify the patterns with the highest wafer sensitivity, rank the hotspots, and translate that sensitivity into mask and wafer metrology requirements. This closes a critical loop: m