A robot cannot wait for a cloud server to decide how to move its arm. A drone must correct its flight in real-time to stay stable, while a motor drive needs to respond to changing loads without missing its control deadline. In these systems, artificial intelligence (AI) has to do more than interpret data: it must work within the timing, power and memory limits of the hardware controlling the machine. That is changing the demands on edge AI, according to Giuseppe Desoli, PhD, Chief Innovation Officer at STMicroelectronics. The company has spent years developing AI capabilities for microcontrollers (MCUs), sensors, connectivity, and embedded processing. The move towards what is increasingly called Physical AI is pushing it to look beyond inference performance and consider how an entire system senses, processes information and acts. Giuseppe Desoli, PhD, Chief Innovation Officer at STMicroelectronics “For a decade our edge-AI work was essentially about perception: classify an image, recognize a gesture, classify a vibration, wake on a keyword. The unit of value was an inference,” Desoli told EE Times Asia . “Physical AI changes that unit. The machine now must perceive, reason, and act inside a control loop whose deadline is set by the physical world; a drone correcting attitude and avoid obstacles, a robotic hand manipulator closing on a deformable object, an inverter reacting to a load transient.” For chip designers, the change is practical. A system may need to combine sensor data, neural-network processing and conventional real-time control while operating within a fixed power budget. Latency and predictable execution matter as much as raw computing throughput. Sensing and actuation also have to be considered alongside the processor rather than treated as separate functions. ST is addressing these issues through its work on embodied AI, including a research program with the National University of Singapore (NUS). Launched in August 2026, the ST–NUS HELIX Corporate Lab — short for Hardware for Embodied Low-power Intelligent Xcceleration — is a four-year initiative focused on edge AI technologies. HELIX takes a system-to-silicon approach, covering algorithms, software and compilers, processor architecture, accelerators, memory, circuits and process technology. The aim is to make design decisions across these areas together, rather than optimize each part in isolation. Desoli argues that the difference can be substantial. “It is not a nice-to-have; it is the only route to the numbers embodied AI demands. The efficiency gap between a naive implementation and a properly co-designed one is one to two orders of magnitude, and you cannot recover that at any single layer of the stack,” he said. A neural network may be quantized to reduce its computational requirements, for example, but the resulting gains depend on how data is stored and moved. Accelerator design also has to account for how the compiler schedules workloads, including attention operations used by transformer-based models. Decisions made separately can lead to higher power consumption or unnecessary silicon area. ST’s position as an integrated device manufacturer gives the company scope to investigate these trade-offs across the stack. It can vary the model, dataflow, memory array and process option, then evaluate the effects using the same test vehicle. Customer applications can also help determine which problems are worth pursuing. Desoli describes model sparsity, caching intermediate data, and storing weights in non-volatile memory close to the compute as connected design choices, not independent techniques. Each affects accuracy, latency and energy use. The collaboration with NUS is intended to combine academic research with the constraints of product development. For embedded AI, a promising algorithm is only part of the work. It must run efficiently on real silicon, fit within a system’s power budget and be supported by software that developers can use. Generative