H.-S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. Credit: DIGITIMES
Breaking AI's memory wall: former TSMC VP charts a path with HBM, optical links and 3D stacking
AI processor performance continues to improve, but memory bandwidth is growing more slowly, making data supply a major constraint on AI chip performance and energy efficiency. Efforts to shorten the distance between memory and compute units and increase die-to-die interconnect density are driving advances in HBM, advanced packaging and 3D integration.
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https://www.digitimes.com/news/a20261021PD215/hbm-3d-bandwidth-data-performance.html
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