By Vladimir Stojanovic and Igor Elkanovich The CPO revolution is at our doorstep. But transforming data center interconnects requires overcoming new challenges in architecture, power delivery, mechanical design, and thermal management. Of these, thermal management has emerged as one of the most critical areas for successfully deploying co-packaged optics (CPO) in hyperscale AI environments. Thermal instability has been a concern for CPO technology. Ayar Labs and Global Unichip Corp. (GUC) jointly conducted thermal co-simulation of the advanced package design and determined the thermal floor map for the package and subsequent chiplets, including air- and liquid-cooled environments. Since thermal stability has been raised as a concern for micro-ring-based CPO, we want to address it head-on. Our co-simulation data show that CPO can operate reliably within the thermal envelope of advanced multi-chip packages. We’re sharing these results to give hyperscalers the confidence to move forward with CPO deployments at scale. Novel design enables over 100 Tbps speeds Let’s start with the new multi-chip package (MCP) design that integrates Ayar Labs’ TeraPHY optical engines into GUC’s advanced packaging and ASIC workflow. The new XPU MCP design replaces traditional electrical interconnects with Ayar Labs’ optical engines, which are attached directly to the MCP organic substrate. This architecture enables a full-duplex optical interface of more than 100 Tbps from the XPU package, an improvement of more than an order of magnitude over current XPUs. UCIe-S provides bandwidth between the optical engines and the I/O chiplets over the MCP substrate. UCIe-A, on the other hand, is used for communication between the I/O chiplet and the main AI die over local silicon interconnect (LSI) bridges. The scale of this design creates thermal challenges we must address. The complete package measures 105mm x 140mm, housing: 2 XPUs (25.69mm x 32.40mm each) 8 HBM4 memory modules 4 I/O chiplets 8 TeraPHY optical engines (12.5mm x 13.0mm each) The +3 kW power envelope in a single package underscores the importance of thermal management and the need for optical engines to operate reliably alongside high-power AI processors. This complex multi-chip architecture requires sophisticated packaging. The design uses a 9-2-9 layer substrate structure to handle the complex routing requirements. The design also addresses signal and power integrity challenges associated with the large-scale package. We perform thermal optimization at the XPU MCP level, while a stiffener design incorporates optical engines’ requirements and enables detachable fiber connections that meet mechanical stress and warpage requirements. What is thermal co-simulation and why is it important? Thermal co-simulation is the combined simulation of electrical behavior and heat flow across a chip. It lets designers predict temperatures, hotspots, and reliability issues in integrated circuits (ICs) and packages under realistic operating conditions. The data ensures the entire system operates within required temperature specifications. This is critical for successful deployment. In GUC’s thermal integrity design flow, we consider every chip’s power maps and perform thermal crosstalk and dynamic thermal co-simulation to ensure the MCP’s thermal integrity from early-stage through sign-off. This allows us to identify local thermal hotspots and the impact of thermal crosstalk on the optical engine. Thermal co-simulation is crucial for GUC’s advanced ASIC workflows. In our joint analysis, the MCP includes multiple chiplets to analyze thermal crosstalk between adjacent chiplet dies. Any heat generated by the entire interposer complex may affect the optical engine’s performance. Thermal modeling is needed to optimize optical engine performance. This joint technical exercise deliberately probes thermal hotspots and thermal crosstalk to evaluate overall CPO thermal stability in a realistic customer package form facto